Titan: Difference between revisions
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|type = Internal/Beta | |type = Internal/Beta | ||
|rarity = Rare | |rarity = Rare | ||
|purpose = | |purpose = Debugger for early XeDK Internal and Beta kits | ||
}} | }} | ||
The Titan board is a debugging board that can only be found in early Xbox 360 XeDK Internal and Beta Development Kits | The Titan board is a debugging board that can only be found in early Xbox 360 XeDK Internal and Beta Development Kits. | ||
__TOC__ | __TOC__ | ||
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== Hardware == | == Hardware == | ||
The Titan board is driven by a Xilinx Spartan XC3S200 Field Programmable Gate Array (FPGA) with an external 50MHz clock. | The Titan board is driven by a Xilinx Spartan XC3S200 Field Programmable Gate Array (FPGA) with an external 50MHz clock. It uses two headers labelled J_YETI and J_GPUL to connect to the VID header (J7G2) and XCPU JTAG header (J8C1) respectively. The J_JTAG header is used to read and write to the FPGA's PROM chip labelled U_PROM. | ||
The J_RISC_WATCH port is used in conjunction with an IBM RISCWatch processor probe in order to debug the XCPU. | The J_RISC_WATCH port is used in conjunction with an IBM RISCWatch processor probe in order to debug the XCPU. | ||
A 4-switch DIP selector is used to configure the FPGA. | A 4-switch DIP selector is used to configure the FPGA. It connects directly to 4 different GPIO pins. Their modes are not currently known. | ||
Earlier models of the Titan board shown in behind-the-scenes videos show that the J_RISCWATCH header had pin 14 missing. | Earlier models of the Titan board shown in behind-the-scenes videos show that the J_RISCWATCH header had pin 14 missing. This pin is labelled as KEY in the RISCWatch datasheet and is not wired on later Titan versions. | ||
Earlier Titans did not have any LEDs present. | |||
Titans that were paired with Internal XeDKs usually had longer wires for J_YETI and J_GPUL most likely in order for the Titan to be used comfortably outside of the console when debugging on a hardware workbench. The extra length on these wires was zip-tied when installed inside of a case. | |||
Titans that were paired with Internal XeDKs usually had longer wires for J_YETI and J_GPUL most likely in order for the Titan to be used comfortably outside of the console when debugging on a hardware workbench. | |||
== Software == | == Software == | ||
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Internal 005 XeDKs had an earlier Titan with a sticker labelled "2005.03.21 VER 00.80". | Internal 005 XeDKs had an earlier Titan with a sticker labelled "2005.03.21 VER 00.80". | ||
Internal 007 XeDKs had | Internal 007 XeDKs had a similar earlier Titan with a sticker labelled "VER 1.7". | ||
== References == | == References == | ||
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File:titan-missing-pin.png|Behind the scenes video showing an earlier Titan with pin 14 missing. Also notice the lack of debug LEDs. | File:titan-missing-pin.png|Behind the scenes video showing an earlier Titan with pin 14 missing. Also notice the lack of debug LEDs. | ||
File:Titan-behind-the-scenes1.PNG|Another look at the early Titan from the behind the scenes video. Notice the same round ROM version sticker. | File:Titan-behind-the-scenes1.PNG|Another look at the early Titan from the behind the scenes video. Notice the same round ROM version sticker. | ||
File:Titan-internal007.png|The Titan of an internal 007 | File:Titan-internal007.png|The Titan of an internal 007 kit. Notice the longer cables and lack of debug LEDs. | ||
File:titan-powered.jpg|The Titan board when powered by an XeDK | File:titan-powered.jpg|The Titan board when powered by an XeDK | ||
File:Ibm-riscwatch1.jpg|An IBM branded RISCWatch processor probe that would be used with the J_RISC_WATCH header. | File:Ibm-riscwatch1.jpg|An IBM branded RISCWatch processor probe that would be used with the J_RISC_WATCH header. |
Latest revision as of 21:52, 8 June 2023
The Titan board is a debugging board that can only be found in early Xbox 360 XeDK Internal and Beta Development Kits.
History
Hardware
The Titan board is driven by a Xilinx Spartan XC3S200 Field Programmable Gate Array (FPGA) with an external 50MHz clock. It uses two headers labelled J_YETI and J_GPUL to connect to the VID header (J7G2) and XCPU JTAG header (J8C1) respectively. The J_JTAG header is used to read and write to the FPGA's PROM chip labelled U_PROM.
The J_RISC_WATCH port is used in conjunction with an IBM RISCWatch processor probe in order to debug the XCPU.
A 4-switch DIP selector is used to configure the FPGA. It connects directly to 4 different GPIO pins. Their modes are not currently known.
Earlier models of the Titan board shown in behind-the-scenes videos show that the J_RISCWATCH header had pin 14 missing. This pin is labelled as KEY in the RISCWatch datasheet and is not wired on later Titan versions.
Earlier Titans did not have any LEDs present.
Titans that were paired with Internal XeDKs usually had longer wires for J_YETI and J_GPUL most likely in order for the Titan to be used comfortably outside of the console when debugging on a hardware workbench. The extra length on these wires was zip-tied when installed inside of a case.
Software
The Titan that shipped with Beta XeDK 007 kits had a firmware sticker labelled "VER 2.11".
Internal 005 XeDKs had an earlier Titan with a sticker labelled "2005.03.21 VER 00.80".
Internal 007 XeDKs had a similar earlier Titan with a sticker labelled "VER 1.7".
References
Gallery
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