XCPU

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XCPU

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{{#if:Xbox 360 Engineering Sample XCPU|

Xbox 360 Engineering Sample XCPU
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Type Internal/Beta/Retail
Purpose Central Processing Unit
Rarity Common

The Microsoft XCPU is the CPU used in all Xbox 360 board revisions. It is based on IBM's PowerPC instruction set architecture. The XCPU contains 3 processor cores with each supporting two symmetric hardware threads. Each core has 32KiB of L1 instruction cache and 32KiB of L1 data cache.

The XCPU was developed by Microsoft and IBM under the project codenamed "Waternoose" (from Henry J. Waternoose III in Monsters, Inc.) Its development was announced on 2003-11-03.

History[edit]

Hardware[edit]

The Xbox 360 S introduced the XCGPU, which integrated the Xenon CPU and the Xenos GPU onto the same die, and the eDRAM into the same package. The XCGPU follows the trend started with the integrated EE+GS in PlayStation 2 Slimline, combining CPU, GPU, memory controllers and IO in a single cost-reduced chip. It also contains a "front side bus replacement block" that connects the CPU and GPU internally in exactly the same manner as the front side bus would have done when the CPU and GPU were separate chips, so that the XCGPU doesn't change the hardware characteristics of the Xbox 360.

XCGPU contains 372 million transistors and is manufactured by GlobalFoundries on a 45 nm process. Compared to the original chipset in the Xbox 360 the combined power requirements are reduced by 60% and the physical chip area by 50%.<ref name="ArsXCGPU">{{#if: {{#if:https://arstechnica.com/gaming/news/2010/08/microsoft-beats-intel-amd-to-market-with-cpugpu-combo-chip.ars | {{#if:Microsoft beats Intel, AMD to market with CPU/GPU combo chip|1}}}}

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Specifications[edit]

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  • 165 million transistors
  • Three cores, each two-way SMT-capable and clocked at 3.2 GHz<ref name="xbox360cpu"/>
  • SIMD: Two VMX128 units with a dedicated (128×128 bit) register file for each core,<ref name="xbox360cpu"/> one for each thread
  • MB L2 cache<ref name="xbox360cpu"/> (lockable by the GPU) running at half-speed (1.6 GHz) with a 256-bit bus
  • 51.2 GB/s of L2 memory bandwidth (256 bit × 1600 MHz)
  • 21.6 GB/s front-side bus (On the CPU side, this interfaces to a 1.35 GHz, 8B wide, FSB dataflow; on the GPU side, it connects to a 16B wide FSB dataflow running at 675 MHz.)<ref name="xbox360cpu"/>
  • Dot product performance: 9.6 billion per second
  • In-order instruction execution<ref name="xbox360cpu"/>
  • 768 bits of IBM eFUSE-based OTP memory<ref name="google">{{#if: {{#if:https://www.youtube.com/watch?v=uxjpmc8ZIxM | {{#if:Xbox360 security system|1}}}}
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  • ROM (and 64 KB SRAM) storing Microsoft's Secure Bootloader, and encryption hypervisor<ref name="google"/>
  • Big-endian architecture

References[edit]

<references />

Gallery[edit]

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