Memory: Difference between revisions
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* 700 MHz DDR | * 700 MHz DDR | ||
** Effective transmission rate of 1.4 GHz on the 128-bit bus | ** Effective transmission rate of 1.4 GHz on the 128-bit bus | ||
* Unified | * Unified Memory Architecture (GPU & CPU Access) | ||
** GPU 10MB eDRAM | ** GPU 10MB eDRAM | ||
* 128-bit interface to ATI's memory controller | * 128-bit interface to ATI's memory controller | ||
== Memory Bandwidth == | == Memory Bandwidth == | ||
* 32 GB/s GPU to eDRAM bandwidth | * 32 GB/s GPU to eDRAM bandwidth | ||
** 2 GHz @ 2 accesses per clock cycle on a 64 bit DDR bus | ** 2 GHz @ 2 accesses per clock cycle on a 64 bit DDR bus | ||
* 22.4 GB/s memory interface bus bandwidth (low latency path to CPU cores) | * 22.4 GB/s memory interface bus bandwidth (low latency path to CPU cores) | ||
** 700 MHz @ 2 accesses per clock cycle (one per edge) on a 128 bit bus | ** 700 MHz @ 2 accesses per clock cycle (one per edge) on a 128 bit bus | ||
* 256 GB/s memory bandwidth to | * 256 GB/s memory bandwidth to eDRAM | ||
* 21.6 GB/s front-side bus | * 21.6 GB/s front-side bus | ||
* Southbridge bandwidth of 500 MB/s. | * [[Southbridge]] bandwidth of 500 MB/s. | ||
[[Category:Hardware]] | [[Category:Hardware]] | ||
Revision as of 22:00, 9 August 2010
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System Memory - Mainboard & GPU
- 512 MB of Unified GDDR3 RAM
- Unified Memory Architecture
- Reduces cost and complexity of the motherboard design
- 700 MHz DDR
- Effective transmission rate of 1.4 GHz on the 128-bit bus
- Unified Memory Architecture (GPU & CPU Access)
- GPU 10MB eDRAM
- 128-bit interface to ATI's memory controller
Memory Bandwidth
- 32 GB/s GPU to eDRAM bandwidth
- 2 GHz @ 2 accesses per clock cycle on a 64 bit DDR bus
- 22.4 GB/s memory interface bus bandwidth (low latency path to CPU cores)
- 700 MHz @ 2 accesses per clock cycle (one per edge) on a 128 bit bus
- 256 GB/s memory bandwidth to eDRAM
- 21.6 GB/s front-side bus
- Southbridge bandwidth of 500 MB/s.